1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a digit line redundancy circuit.
2. Description of the Related Art
In a conventional semiconductor memory there may be found a digit line redundancy circuit having a digit line substitution address programming circuit. In such a semiconductor memory, redundant digit lines are used instead of the digit lines corresponding to input column addresses when the address programming circuit generates a redundancy signal. The digit line substitution address programming circuit is programmed by melting a fuse corresponding to the address of a defective digit line, discovered by electrical, laser irradiation or other types of inspection.
The operation of a conventional semiconductor memory device with a digit line redundancy circuit is as follows. First, the digit line substitution address programming circuit generates a redundancy signal when an input column address corresponds to the address of a defective digit line. In response to this redundancy signal, an enable signal for a column decoder goes to an inactive state, and a redundant digit line selection signal is activated. Since the enable signal for the column decoder is in an inactive state at this time, digit line selection signals all go to the inactive state, so that the input/output (IO) lines and the digit lines corresponding to the input column address are not connected. Accordingly, only the redundant digit lines are connected to the IO lines for a data write/read operation.
However, in the conventional digit line redundancy circuit mode, where selection is made between connecting the digit lines or the redundant digit lines to the same IO lines, there is a possibility of generating a multiple selected state in which the digit lines and the redundant digit lines are connected simultaneously to identical IO lines. That is, a redundant digit line selection signal is activated in response to the redundancy signal generated by the digit line substitution address programming circuit, but at the same time the enable signal for the column decoder starts to go to the inactive state, namely, the generation of the digit line selection signal of the column decoder begins to be inhibited. Accordingly, since the time of activation of the redundant digit line selection signal is simultaneous with the time of inactivation of the enable signal for the column decoder, there is a possibility of an instantaneous occurrence, at this time, of a multiple selected state in which the digit line selection signal and the redundant digit line selection signal are simultaneously in the active state. When the multiple selected state occurs, data on the IO lines become erroneous, and therefore the memory malfunctions.
Further, let us consider what happens when the selected state of the redundant digit lines goes to the selected state of the normal bit lines. The circuit which judges that the normal digit lines are selected with a change in column addresses is also the digit line substitution address programming circuit. It is this circuit which changes the redundancy signal from the active state to the inactive state in response to the input column addresses. In response to this change, the enable signal for the column decoder goes from the inactive state to the active state, causing the column decoder to operate. In other words, in the operation of returning to the normal digit lines, the column decoder is operated only after the change in the redundancy signal so that there is a problem that the activation and the operation of the column decoder are delayed.